Static random access memory (SRAM) devices may be designed for providing acceptable read stability and/or write margins. As the technology advances, however, designing such margins has been increasingly difficult due at least in part to the scaling down of the minimum feature sizes of the transistors. The speed gain of the transistors, although desirable, has resulted in an increase in leakage current. In a memory array, comprising multiple SRAM cells, the leakage current may be amplified, which may result in an unacceptable level of power consumption and/or functional failures.
Measures taken to minimize the current leakage may, unfortunately, negatively impact the writeability of the SRAM cells. To compensate for the reduced writeability, various measures have been attempted including, for example, slowing down the write access and/or raising the operating voltage of the SRAM cell. Unfortunately, slowing down the write access to the SRAM cell may affect overall speed, while raising the operating voltage may affect the power consumption.
Various methods that attempted to overcome the foregoing write margin issues may nevertheless be inadequate for optimizing the SRAM design. For example, some methods are directed to increasing the word line voltage above the power supply voltage, but this may result in an increase in power consumption. Another method is directed to raising a local ground voltage to a voltage substantially equal to a global ground voltage, but this may require an increased silicon area by increasing the size of the SRAM cell itself. Further, the time for raising the local ground voltage may be slow due to slow current charging of the local ground.